Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS) technology. The capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors slowly leaks off, so without intervention the data on the chip would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory (vs. non-volatile memory), since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.
DRAM typically takes the form of an integrated circuit chip, which can consist of dozens to billions of DRAM memory cells. DRAM chips are widely used in digital electronics where low-cost and high-capacity computer memory is required. One of the largest applications for DRAM is the main memory (colloquially called the "RAM") in modern computers and graphics cards (where the "main memory" is called the graphics memory). It is also used in many portable devices and video game consoles. In contrast, SRAM, which is faster and more expensive than DRAM, is typically used where speed is of greater concern than cost and size, such as the cache memories in processors.
Due to its need of a system to perform refreshing, DRAM has more complicated circuitry and timing requirements than SRAM, but it is much more widely used. The advantage of DRAM is the structural simplicity of its memory cells: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities, making DRAM much cheaper per bit. The transistors and capacitors used are extremely small; billions can fit on a single memory chip. Due to the dynamic nature of its memory cells, DRAM consumes relatively large amounts of power, with different ways for managing the power consumption.
DRAM had a 47% increase in the price-per-bit in 2017, the largest jump in 30 years since the 45% jump in 1988, while in recent years the price has been going down.
Dynamic random-access memory (DRAM) is a type of random-access semiconductor memory that stores each bit of data in a memory cell consisting of a tiny capacitor and a transistor. The capacitor can either be charged or discharged; however, The electric charge on the capacitors slowly leaks off, so without intervention the data on the chip would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. The advantage of DRAM is the structural simplicity of its memory cells: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities, making DRAM much cheaper per bit.
DRAM vs Flash
- DRAM is volatile memory and needs a refreshing circuit to keep periodically refreshing the exiting value of the capacitor the primary memory which does most of the process work and supplies the data to CPU which, then, reads/writes back to permanent memory. Due to its minimalist structure, it provides greater memory density at relatively faster speeds but is more expensive.
- Non Volatile Memory (NVM) is used as a permanent storage (secondary storage) which can retain/hold the data when the power is down and the internal structures are NAND/NOR cells. While DRAM provides the flexibility to read/write in bits (Bit line and Word Line), FLASH forces you to erase the data in entire block of word even if few bits are to be erased but is cheaper.
Ranks and Banks
1Rx?? means it is a single-rank module and 2Rx?? means it is a dual-rank module module. Rank is a data block which is 64 bits wide without Error Correction Code (ECC) created using some, or all of the memory chips on a module. More ranks allows more banks to be kept open, which could reduce average memory latency. However, more ranks may require looser timings because there are more chips connected to the same lines on the DRAM bus.
The x?? in them specifies the number of banks in the memory module. Higher the number of banks, the fewer the chips in the memory module, the better the reliability and power consumption.
Single- vs Dual-Channel
RAM communicates with the CPU through the memory controller on the CPU. Most modern motherboards have two 64-bit (total 128-bit) channels between the CPU and memory. In a single-channel configuration, only one of them is functional. This limits memory throughput to the rated speed of the slowest single RAM module installed. In dual-channel memory configurations, the memory controller uses both the channels to communicate with the CPU, essentially doubling the bandwidth.
For example, Single-channel 2133 MHz DDR4 delivers 17 GB/s of memory bandwidth. If you have a pair of 2133 MHz DDR4 modules in dual-channel, your memory bandwidth doubles to 34 GB/s. The only way to hit that level of performance in single-channel mode is to use memory modules running at 4000 MHz or higher.
ECC vs Non-ECC Memory
As businesses depend more on big data, the need to prevent data loss is critical. One of the most vital areas for this loss prevention is where data is temporarily stored, DRAM. ECC, or Error-Correcting Code, protects your system from potential crashes and inadvertent changes in data by automatically correcting data errors. This is achieved with the addition of another chip on the DRAM module, which acts as an error check and correction for the other DRAM chips. While marginally more expensive than non-ECC RAM, the added protection it provides is critical for financial information or critical personal information, especially medical, where any data loss or transcription error is unacceptable.
Raw Cards and DRAM Organizations
The Joint Electron Device Engineering Council (JEDEC) has defined a full range of module configurations that generate a standardized base for all DDR SODIMMs. There are primarily four types of cards: the single-rank module built with x8 DRAM; the singlerank module built with x16 DRAM; the dual-rank module built with x8 DRAM; and the dual-rank module built with x16 DRAM. These cards have been designed to work in a single-channel, dual-slot memory system with either one or many of the two cards populated. For DDR4, these Raw Cards are defined as follows.
|Raw Card||DRAM Chips||DRAM Organization||ECC / Non-ECC||Chip Positioning|